1. Field of the Invention
The present invention relates to the area of data transmission between a source device and a destination device, and more particularly to data transmission between the source device and the destination device via a direct memory access controller with minimum impact on the CPU.
2. Description of Related Art
Direct memory access (DMA) is a feature of modern computers, that allows certain hardware subsystems within the computer to access system memory for reading and/or writing independently of the central processing unit. Many hardware systems use DMA including disk drive controllers, graphics cards, network cards, and sound cards. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without a DMA channel. However, the DMAC can only transmit data with continuous addresses at one time. For the mass data without continuous addresses, a Direct Memory Access Controller (DMAC) has to transmit them in batches according to their respective continuous addresses and requires to be reconfigured by the CPU during each batch of the DMA transmission. In other words, the DMAC has to repeatedly interrupt the CPU's execution on other tasks to get continuation address in the DMA transmission, thus adding additional burdens to the CPU.
Additionally, there will be a plurality of functional devices to request the DMAC for the DMA transmissions each of which corresponds to a DMAC channel. The CPU has to be interrupted to switch among different DMA channels. If the switch between the different DMA channels is high frequently, it would further add additional burdens to the CPU.
Thus, there is a need for techniques for transmitting data more efficiently via the DMAC with minimum impact on a CPU.